Habe eine Nokia Sat mit 2xa
dbug enabled (nach längerem hin und her)
beim image flashen (alexW2xBaseimageV1.6.img) kommt folgendes
]debug: DDF: Calibrating delay loop... debug: DDF: 67.79 BogoMIPS
debug: BMon V1.0 mID 01
debug: feID dd gtxID 00
debug: fpID 5a dsID 01-dc.09.02.07.00.00-0a
debug: HWrev X5 SWrev 0.81
debug: B/Ex/Fl(MB) 16/16/08
WATCHDOG reset enabled
dbox2:root> debug:
BOOTP/TFTP bootstrap loader (v0.3)
debug:
debug: Transmitting BOOTP request via broadcast
debug: Got BOOTP reply from Server IP 192.168.0.1, My IP 192.168.0.23
debug: Sending TFTP-request for file C/DBoxBoot/ppcboot_writeflash
will verify ELF image, start= 0x800000, size= 201596
verify sig: 262
boot net: boot file has no valid signature
Branching to 0x40000
ppcboot 0.6.4 (Apr 11 2002 - 16:10:44)
Initializing...
CPU: PPC823ZTnnA at 67 MHz: 2 kB I-Cache 1 kB D-Cache
*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
Board: ### No HW ID - assuming TQM8xxL
DRAM: (faked) 32 MB
Ethernet: 00-50-9c-13-2e-ca
FLASH: 8 MB
LCD driver (KS0713) initialized
BOOTP broadcast 1
TFTP from server 192.168.0.1; our IP address is 192.168.0.23
Filename 'C/tftpboot/logo-lcd'.
Load address: 0x130000
Loading: ##

LCD logo at: 0x130000 (0x1F9FFC0 bytes)
BOOTP broadcast 1
TFTP from server 192.168.0.1; our IP address is 192.168.0.23
Filename 'C/tftpboot/logo-fb'.
Load address: 0x120000
Loading: #########

FB logo at: 0x0 (0x1FC0000 bytes)
debug: DDF: Calibrating delay loop... debug: DDF: 67.79 BogoMIPS
debug: WATCHDOG RESET
debug: BMon V1.0 mID 01
debug: feID dd gtxID 00
debug: fpID 5a dsID 01-dc.09.02.07.00.00-0a
debug: HWrev X5 SWrev 0.81
debug: B/Ex/Fl(MB) 16/16/08
WATCHDOG reset enabled
dbox2:root> debug:
BOOTP/TFTP bootstrap loader (v0.3)
debug:
debug: Transmitting BOOTP request via broadcast
debug: Got BOOTP reply from Server IP 192.168.0.1, My IP 192.168.0.23
debug: Sending TFTP-request for file C/DBoxBoot/ppcboot_writeflash
will verify ELF image, start= 0x800000, size= 201596
verify sig: 262
boot net: boot file has no valid signature
Branching to 0x40000
ppcboot 0.6.4 (Apr 11 2002 - 16:10:44)
Initializing...
CPU: PPC823ZTnnA at 67 MHz: 2 kB I-Cache 1 kB D-Cache
*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
Board: ### No HW ID - assuming TQM8xxL
DRAM: (faked) 32 MB
Ethernet: 00-50-9c-13-2e-ca
FLASH: 8 MB
LCD driver (KS0713) initialized
BOOTP broadcast 1
TFTP from server 192.168.0.1; our IP address is 192.168.0.23
Filename 'C/tftpboot/logo-lcd'.
Load address: 0x130000
Loading: ##

LCD logo at: 0x130000 (0x1F9FFC0 bytes)
BOOTP broadcast 1
TFTP from server 192.168.0.1; our IP address is 192.168.0.23
Filename 'C/tftpboot/logo-fb'.
Load address: 0x120000
Loading: #########

FB logo at: 0x0 (0x1FC0000 bytes)
debug: DDF: Calibrating delay loop... debug: DDF: 67.79 BogoMIPS
debug: WATCHDOG RESET
debug: BMon V1.0 mID 01
debug: feID dd gtxID 00
debug: fpID 5a dsID 01-dc.09.02.07.00.00-0a
debug: HWrev X5 SWrev 0.81
debug: B/Ex/Fl(MB) 16/16/08
WATCHDOG reset enabled
dbox2:root> debug:
BOOTP/TFTP bootstrap loader (v0.3)
debug:
debug: Transmitting BOOTP request via broadcast
debug: Got BOOTP reply from Server IP 192.168.0.1, My IP 192.168.0.23
debug: Sending TFTP-request for file C/DBoxBoot/ppcboot_writeflash
will verify ELF image, start= 0x800000, size= 201596
verify sig: 262
boot net: boot file has no valid signature
Branching to 0x40000
ppcboot 0.6.4 (Apr 11 2002 - 16:10:44)
Initializing...
CPU: PPC823ZTnnA at 67 MHz: 2 kB I-Cache 1 kB D-Cache
*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
Board: ### No HW ID - assuming TQM8xxL
DRAM: (faked) 32 MB
Ethernet: 00-50-9c-13-2e-ca
FLASH: 8 MB
LCD driver (KS0713) initialized
BOOTP broadcast 1
TFTP from server 192.168.0.1; our IP address is 192.168.0.23
Filename 'C/tftpboot/logo-lcd'.
Load address: 0x130000
Loading: ##

LCD logo at: 0x130000 (0x1F9FFC0 bytes)
BOOTP broadcast 1
TFTP from server 192.168.0.1; our IP address is 192.168.0.23
Filename 'C/tftpboot/logo-fb'.
Load address: 0x120000
Loading: #########

FB logo at: 0x0 (0x1FC0000 bytes)
debug: DDF: Calibrating delay loop... debug: DDF: 67.79 BogoMIPS
debug: WATCHDOG RESET
debug: BMon V1.0 mID 01
debug: feID dd gtxID 00
debug: fpID 5a dsID 01-dc.09.02.07.00.00-0a
debug: HWrev X5 SWrev 0.81
debug: B/Ex/Fl(MB) 16/16/08
WATCHDOG reset enabled
dbox2:root> debug:
BOOTP/TFTP bootstrap loader (v0.3)
debug:
debug: Transmitting BOOTP request via broadcast
debug: Got BOOTP reply from Server IP 192.168.0.1, My IP 192.168.0.23
debug: Sending TFTP-request for file C/DBoxBoot/ppcboot_writeflash
will verify ELF image, start= 0x800000, size= 201596
verify sig: 262
boot net: boot file has no valid signature
Branching to 0x40000
ppcboot 0.6.4 (Apr 11 2002 - 16:10:44)
Initializing...
CPU: PPC823ZTnnA at 67 MHz: 2 kB I-Cache 1 kB D-Cache
*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
Board: ### No HW ID - assuming TQM8xxL
DRAM: (faked) 32 MB
Ethernet: 00-50-9c-13-2e-ca
FLASH: 8 MB
LCD driver (KS0713) initialized
BOOTP broadcast 1
TFTP from server 192.168.0.1; our IP address is 192.168.0.23
Filename 'C/tftpboot/logo-lcd'.
Load address: 0x130000
Loading: ##

LCD logo at: 0x130000 (0x1F9FFC0 bytes)
BOOTP broadcast 1
TFTP from server 192.168.0.1; our IP address is 192.168.0.23
Filename 'C/tftpboot/logo-fb'.
Load address: 0x120000
Loading: #########

FB logo at: 0x0 (0x1FC0000 bytes)
debug: DDF: Calibrating delay loop... debug: DDF: 67.79 BogoMIPS
debug: WATCHDOG RESET
debug: BMon V1.0 mID 01
Irgendwie kommt da ein RESET daher und alles fängt von vorne an.
Und das immer wieder und wieder .........
Hat vielleicht jemand eine Idee dazu?